1. Field of Invention
The present invention relates to a chip package structure and a method for manufacturing the chip package structure. More particularly, the present invention relates to a method for manufacturing a wafer level chip scale package structure with a compact size.
2. Description of Related Art
Chip scale package (CSP) is a package that has an area of no more 20% larger than that of the die. With better protection by molding encapsulation and better board level reliability, CSP prevails over the direct chip attach (DCA) and chip on board (COB) technologies.
Taking chip scale packaging process as an example, the backs of the chips are attached to the substrate and the chips are electrically connected to the substrate through wire bonding. The chips and the substrate are simultaneously encapsulated by the encapsulating material in transfer molding process. After performing singulation by dicing, a plurality of chip package structures is obtained. FIG. 1 is a cross-sectional view of the prior art CSP structure after dicing. Referring to FIG. 1, one chip package structure 102 includes the substrate 110, the chip (die) 130 and the molding compound 170. In general, the back of chip 130 is glued onto the substrate 110 by silver epoxy, and the chip (from the top surface) is electrically connected to the substrate 110 through wires 180 by wire bonding. The chip 130 and wires 180 are covered by the molding compound 170 formed by encapsulation. The substrate 110 further includes solder balls 190 on the bottom for external electrical connection. Due to the application of wires and the molding compound, the package structure is somehow larger and thicker than the chip itself. In general, the size (area) of CSP package is about 20% larger than the die and the height (thickness) of CSP package is around 1.2 mm.
However, issues around the reliability of the packaging still remain. For the package structure comprised of silicon chip, bismaleimide triazine (BT) substrate, the molding compound and silver epoxy, it would encounter various stress-related problems due to different coefficient of thermal expansion (CTE). For the prior art CSP structure, the CTE mismatch between the package substrate and the silicon chip is large (about 14 ppm) thus lowering the reliability and quality of the package structure. Moreover, the fabrication processes of the prior art CSP structure are complex and the widely used BT substrate is quite costly.